//======================================================================================================
// State Machine
// 2011-11-08
// James Young
`timescale      1ns/10ps
`define         dS_IDLE         2'b00
`define         dS_START        2'b01
`define         dS_STOP         2'b10
`define         dS_CLEAR        2'b11
//======================================================================================================
module          TestState
                (
                Reset,
                CLK,
                A,
                F,
                G,
                ) ;
//------------------------------------------------------------------------------------------------------
input           Reset ;
input           CLK ;
input           A ;
input           F ;
input           G ;
//------------------------------------------------------------------------------------------------------
reg     [1:0]   State ;
//------------------------------------------------------------------------------------------------------
always  @(posedge CLK or negedge Reset)
        begin
        if (~Reset)
                begin
                State   <= `dS_IDLE ;
                end
        else
                begin
                case    (State [1:0])
                        `dS_IDLE:
                                begin
                                if ((A == 1'b1) || (G == 1'b0))
                                        begin
                                        State   <= `dS_START ;
                                        end
                                end

                        `dS_START:
                                begin
                                if (A == 1'b0)
                                        begin
                                        State   <= `dS_STOP ;
                                        end
                                else if ((F == 1'b0) && (G == 1'b0))
                                        begin
                                        State   <= `dS_IDLE ;
                                        end
                                end

                        `dS_STOP:
                                begin
                                if ((A == 1'b1) || (F == 1'b1))
                                        begin
                                        State   <= `dS_CLEAR ;
                                        end
                                else if ((F == 1'b0) && (G == 1'b0))
                                        begin
                                        State   <= `dS_IDLE ;
                                        end
                                end

                        `dS_CLEAR:
                                being
                                if (((A == 1'b0) || (F == 1'b0)) && (G == 1'b1))
                                        begin
                                        State   <= `dS_IDLE ;
                                        end
                                end
                endcase
                end
        end
//------------------------------------------------------------------------------------------------------
endmodule
//======================================================================================================