#include "config.h"
#include "si4432.h"
#include "time.h"
#include "spi.h"
#include "fsprint.h"
#include "string.h"


 /*-------------------------------------------------------------------------
 *  <Function>
 * 		初始化芯片
 *  <Parameter>
 * 		None
 *  <Return>
 *  	None
 * -----------------------------------------------------------------------*/
void init_si4432(void)
{
	U8 ItStatus1, ItStatus2;

	// SW reset
	si4432_write_reg(0x07, 0x80);

	//wait for chip ready interrupt from the radio
	while(INT0 == 1);

	//read interrupt status register to clear the interrupt flags and release the interrupt
	ItStatus1 = si4432_read_reg(0x03);
	ItStatus2 = si4432_read_reg(0x04);

	//-------------------------------------------------------
	// set RF Parameters
	//-------------------------------------------------------
	/* set the physical parameters*/
	// set the center frequency to 433MHz
	si4432_write_reg(0x75, 0x53);  //write 0x53 to the Frequency Band Select register (sbsel=1, hbsel=0, fb[4:0]=0x13
	si4432_write_reg(0x76, 0x4B);  //write 0x4B to the Nominal Carrier Frequency1 register
	si4432_write_reg(0x77, 0x00);  //write 0x00 to the Nominal Carrier Frequency0 register


	// set the desired TX data rate = 2.4kbps
	si4432_write_reg(0x6E, 0x13);  //write the TXDataRate 1 register according to the bps
	si4432_write_reg(0x6F, 0xa9);  //write the TXDataRate 0 register according to the bps
	si4432_write_reg(0x70, 0x2c);    //write the Modulation Mode Control 1 register according to the bps

	
	/*set the modem parameters according to the excel calculator(parameters: 2.4 kbps, deviation: 10 kHz, channel filter BW: 22.7kHz
577 kHz*/
	si4432_write_reg(0x1C, 0x23); //write 0x8D to the IF Filter Bandwidth register
	si4432_write_reg(0x20, 0xA1); //write 0xA1 to the Clock Recovery Oversampling Ratio register
	si4432_write_reg(0x21, 0x20); //write 0x20 to the Clock Recovery Offset 2 register
	si4432_write_reg(0x22, 0x4E); //write 0x4E to the Clock Recovery Offset 1 register
	si4432_write_reg(0x23, 0xA4); //write 0xA5 to the Clock Recovery Offset 0 register
	si4432_write_reg(0x24, 0x00); //write 0x00 to the Clock Recovery Timing Loop Gain 1 register
	si4432_write_reg(0x25, 0x27); //write 0x27 to the Clock Recovery Timing Loop Gain 0 register
	si4432_write_reg(0x1D, 0x40); //write 0x40 to the AFC Loop Gearshift Override register
	si4432_write_reg(0x72, 0x10); //write 0x10 to the Frequency Deviation register

	si4432_write_reg(0x69, 0x60); //write 0x60 to the AGC Override 1 register
	si4432_write_reg(0x09, 0xD7); //write 0xD7 to the Crystal Oscillator Load Capacitance register

	//-------------------------------------------------------
	// set packet Parameters
	//-------------------------------------------------------
	/*set the packet structure and the modulation type*/
	//set the preamble length to 10bytes if the antenna diversity is used and set to 5bytes if not
	si4432_write_reg(0x34, 0x0A); //write 0x0A to the Preamble Length register
	//set preamble detection threshold to 20bits
	si4432_write_reg(0x35, 0x28); //write 0x28 to the Preamble Detection Control register
	//Disable header bytes; set variable packet length (the length of the payload is defined by the
	//received packet length field of the packet); set the synch word to two bytes long
	si4432_write_reg(0x33, 0x02); //write 0x02 to the Header Control2 register
	//Set the sync word pattern to 0x2DD4
	si4432_write_reg(0x36, 0x2D); //write 0x2D to the Sync Word 3 register
	si4432_write_reg(0x37, 0xD4); //write 0xD4 to the Sync Word 2 register
	//enable the TX & RX packet handler and CRC-16 (IBM) check
	si4432_write_reg(0x30, 0x8D); //write 0x8D to the Data Access Control register
	//Disable the receive header filters
	si4432_write_reg(0x32, 0x00 ); //write 0x00 to the Header Control1 register

	si4432_write_reg(0x1E, 0x0A);  //write 0x0A to the AFC Timing Control register
	si4432_write_reg(0x2A, 0x1D);  //write 0x1D to the AFC Limiter register
	si4432_write_reg(0x1F, 0x03);  //write 0x03 to the Clock Recovery Gearshift Override register


	//-------------------------------------------------------
	// set modulation Parameters
	//-------------------------------------------------------

	// enable FIFO mode and GFSK modulation 
	si4432_write_reg(0x71, 0xA3);  //write 0xA3 to the Modulation Mode Control 2 register
	si4432_write_reg(0x6D, 0x1F);  //write 0x1F to the TX Power Control register

	//因为电路板和Silicon Labs的demo板接线正好相反
	si4432_write_reg(0x0D, 0x12);  //write 0x12 to the GPIO1 Configuration (set the TX state)
	si4432_write_reg(0x0C, 0x15);  //write 0x15 to the GPIO2 Configuration (set the RX state)

	si4432_write_reg(0x07, 0x05);  //write 0x05 to the Operating Mode and Function Control 1 register
	si4432_write_reg(0x05, 0x03);  //write 0x03 to the Interrupt Enable 1 register
	si4432_write_reg(0x06, 0x00);  //write 0x00 to the Interrupt Enable 2 register
	
}

/*
 * <Function>
 * 		通过SI4432读取一个数据包
 * <Parameter>
 * 		buf:  数据缓冲区指针
 * 	<Return>
 * 		读取的数据长度
 * */
U8 si4432_read(U8 *buf)
{
	U8 i;
	U8 len;
	U8 ItStatus1;	

	if(INT0 == 1) return 0;

	ItStatus1 = si4432_read_reg(0x03);//read the Interrupt Status1 register
	// CRC Error!
	if((ItStatus1&0x01)==0x01)
		return 0;
	if((ItStatus1&0x02)==0x02)
	{
		len = si4432_read_reg(0x4B); //read the received packet length
	
		if (len == 0)
			return 0;
	
		// read the received packet data
		for(i=0; i<len; i++)
			*(buf+i) = si4432_read_reg(0x7F);
	
		// reset the RX FIFO
		si4432_write_reg(0x08, 0x02);
		si4432_write_reg(0x08, 0x00);
	
		si4432_write_reg(0x07, 0x05); //reenter the RX state
	
		si4432_write_reg(0x05, 0x03); //write 0x03 to the Interrupt Enable 1 register
		return len;
	}
}

 
/*
 * <Function>
 * 		通过SI4432发送一个数据包（不大于64字节）
 * <Parameter>
 * 		buf:  数据缓冲区指针
 * 		len: 要发送的字节数
 * 	<Return>
 * 		发送状态
 * */
U8 si4432_send(U8 *buf, U8 len)
{
	U8 i;
	U8 ItStatus1;	
	U8 ItStatus2;	


	if(len > 64)
	{
		return 0;
	}
	//set the length of the payload
	si4432_write_reg(0x3E, len); //write len to the Transmit Packet Length register
	//fill the payload into the transmit FIFO
	for(i=0; i<len; i++)
		si4432_write_reg(0x7F, buf[i]); //write data to the FIFO Access register

	//Disable all other interrupts and enable the packet sent interrupt only.
	//This will be used for indicating the successfull packet transmission for the MCU
	si4432_write_reg(0x05, 0x04); //write 0x04 to the Interrupt Enable 1 register
	si4432_write_reg(0x06, 0x00); //write 0x03 to the Interrupt Enable 2 register
	//Read interrupt status regsiters. It clear all pending interrupts and the nIRQ pin goes back to high.
	ItStatus1 = si4432_read_reg(0x03);//read the Interrupt Status1 register
	ItStatus2 = si4432_read_reg(0x04);//read the Interrupt Status2 register
	/*enable transmitter*/
	//The radio forms the packet and send it automatically.

	si4432_write_reg(0x07, 0x09);//write 0x09 to the Operating Function Control 1 register
	while(INT0 == 1);
	ItStatus1 = si4432_read_reg(0x03);//read the Interrupt Status1 register
	ItStatus2 = si4432_read_reg(0x04);//read the Interrupt Status2 register
	
	return 0;
}