module div_sim
(
    output o,
    input clk,
    input rst

);
    parameter DIV_FACTOR = 16;//分频比
    parameter COUNTER_WIDTH = 32;//DIV_FACTOR所需位宽

	reg[COUNTER_WIDTH-1:0] counter;
	
	assign o = (counter<DIV_FACTOR/2)?1'B1:1'B0;
	
    always@(posedge clk, negedge rst)
	begin		
		if (rst == 1'B0)
        begin
			counter <= 1'B0;
        end
        else if(clk == 1'B1)
        begin
			if (counter == DIV_FACTOR-1)
			    counter <= 1'B0;
			else
    			counter <= counter+1'B1;
		end
	end

endmodule