`timescale 1ns / 1ns

module clock
(
    output  reg clk,
    output  reg rst
);

    parameter CLK_PERIOD = 20;//20ns

    initial
    begin
        #0 clk <= 1'B0; rst <= 1'B1;
        #CLK_PERIOD rst <= 1'B0;
        #(CLK_PERIOD*10) rst <= 1'B1;
    end
    
    always #(CLK_PERIOD/2) clk = ~clk;
   
endmodule