module main(clk, out_data_p1,out_clk_p1,out_rck_p1, out_data_p2,out_clk_p2,out_rck_p2, out_data_p3,out_clk_p3,out_rck_p3, out_data_p4,out_clk_p4,out_rck_p4, out_data_p5,out_clk_p5,out_rck_p5, out_data_p6,out_clk_p6,out_rck_p6, out_data_p7,out_clk_p7,out_rck_p7, out_data_p8,out_clk_p8,out_rck_p8, out_data_p9,out_clk_p9,out_rck_p9, out_data_p10,out_clk_p10,out_rck_p10, out_data_p11,out_clk_p11,out_rck_p11, out_data_p12,out_clk_p12,out_rck_p12, out_data_p13,out_clk_p13,out_rck_p13, out_data_p14,out_clk_p14,out_rck_p14, out_data_p15,out_clk_p15,out_rck_p15, out_data_p16,out_clk_p16,out_rck_p16, out_data_p17,out_clk_p17,out_rck_p17, out_data_p18,out_clk_p18,out_rck_p18, out_data_p19,out_clk_p19,out_rck_p19, out_data_p20,out_clk_p20,out_rck_p20, out_data_p21,out_clk_p21,out_rck_p21, out_data_p22,out_clk_p22,out_rck_p22, out_data_p23,out_clk_p23,out_rck_p23, out_data_p24,out_clk_p24,out_rck_p24, sram_data,sign0,sign1,sign2,sign3); input clk; //for 74hc595_1 output out_data_p1,out_clk_p1,out_rck_p1; //for 74hc595_1 wire spi_data_p1_ws,spi_rck_p1_ws,spi_clk_p1_ws,spi_en_p1_ws,spi_finish_p1_ws,clk_p1_ws; wire[15:0] spi_data16_p1_ws; //assign for spi assign clk_p1_ws = clk; //74hc595 clk signal in assign out_data_p1 = spi_data_p1_ws; //74hc595 data signal out assign out_clk_p1 = spi_clk_p1_ws; //74hc595 clk signal out assign out_rck_p1 = spi_rck_p1_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p2,out_clk_p2,out_rck_p2; //for 74hc595_1 wire spi_data_p2_ws,spi_rck_p2_ws,spi_clk_p2_ws,spi_en_p2_ws,spi_finish_p2_ws,clk_p2_ws; wire[15:0] spi_data16_p2_ws; //assign for spi assign clk_p2_ws = clk; //74hc595 clk signal in assign out_data_p2 = spi_data_p2_ws; //74hc595 data signal out assign out_clk_p2 = spi_clk_p2_ws; //74hc595 clk signal out assign out_rck_p2 = spi_rck_p2_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p3,out_clk_p3,out_rck_p3; //for 74hc595_1 wire spi_data_p3_ws,spi_rck_p3_ws,spi_clk_p3_ws,spi_en_p3_ws,spi_finish_p3_ws,clk_p3_ws; wire[15:0] spi_data16_p3_ws; //assign for spi assign clk_p3_ws = clk; //74hc595 clk signal in assign out_data_p3 = spi_data_p3_ws; //74hc595 data signal out assign out_clk_p3 = spi_clk_p3_ws; //74hc595 clk signal out assign out_rck_p3 = spi_rck_p3_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p4,out_clk_p4,out_rck_p4; //for 74hc595_1 wire spi_data_p4_ws,spi_rck_p4_ws,spi_clk_p4_ws,spi_en_p4_ws,spi_finish_p4_ws,clk_p4_ws; wire[15:0] spi_data16_p4_ws; //assign for spi assign clk_p4_ws = clk; //74hc595 clk signal in assign out_data_p4 = spi_data_p4_ws; //74hc595 data signal out assign out_clk_p4 = spi_clk_p4_ws; //74hc595 clk signal out assign out_rck_p4 = spi_rck_p4_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p5,out_clk_p5,out_rck_p5; //for 74hc595_1 wire spi_data_p5_ws,spi_rck_p5_ws,spi_clk_p5_ws,spi_en_p5_ws,spi_finish_p5_ws,clk_p5_ws; wire[15:0] spi_data16_p5_ws; //assign for spi assign clk_p5_ws = clk; //74hc595 clk signal in assign out_data_p5 = spi_data_p5_ws; //74hc595 data signal out assign out_clk_p5 = spi_clk_p5_ws; //74hc595 clk signal out assign out_rck_p5 = spi_rck_p5_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p6,out_clk_p6,out_rck_p6; //for 74hc595_1 wire spi_data_p6_ws,spi_rck_p6_ws,spi_clk_p6_ws,spi_en_p6_ws,spi_finish_p6_ws,clk_p6_ws; wire[15:0] spi_data16_p6_ws; //assign for spi assign clk_p6_ws = clk; //74hc595 clk signal in assign out_data_p6 = spi_data_p6_ws; //74hc595 data signal out assign out_clk_p6 = spi_clk_p6_ws; //74hc595 clk signal out assign out_rck_p6 = spi_rck_p6_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p7,out_clk_p7,out_rck_p7; //for 74hc595_1 wire spi_data_p7_ws,spi_rck_p7_ws,spi_clk_p7_ws,spi_en_p7_ws,spi_finish_p7_ws,clk_p7_ws; wire[15:0] spi_data16_p7_ws; //assign for spi assign clk_p7_ws = clk; //74hc595 clk signal in assign out_data_p7 = spi_data_p7_ws; //74hc595 data signal out assign out_clk_p7 = spi_clk_p7_ws; //74hc595 clk signal out assign out_rck_p7 = spi_rck_p7_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p8,out_clk_p8,out_rck_p8; //for 74hc595_1 wire spi_data_p8_ws,spi_rck_p8_ws,spi_clk_p8_ws,spi_en_p8_ws,spi_finish_p8_ws,clk_p8_ws; wire[15:0] spi_data16_p8_ws; //assign for spi assign clk_p8_ws = clk; //74hc595 clk signal in assign out_data_p8 = spi_data_p8_ws; //74hc595 data signal out assign out_clk_p8 = spi_clk_p8_ws; //74hc595 clk signal out assign out_rck_p8 = spi_rck_p8_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p9,out_clk_p9,out_rck_p9; //for 74hc595_1 wire spi_data_p9_ws,spi_rck_p9_ws,spi_clk_p9_ws,spi_en_p9_ws,spi_finish_p9_ws,clk_p9_ws; wire[15:0] spi_data16_p9_ws; //assign for spi assign clk_p9_ws = clk; //74hc595 clk signal in assign out_data_p9 = spi_data_p9_ws; //74hc595 data signal out assign out_clk_p9 = spi_clk_p9_ws; //74hc595 clk signal out assign out_rck_p9 = spi_rck_p9_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p10,out_clk_p10,out_rck_p10; //for 74hc595_1 wire spi_data_p10_ws,spi_rck_p10_ws,spi_clk_p10_ws,spi_en_p10_ws,spi_finish_p10_ws,clk_p10_ws; wire[15:0] spi_data16_p10_ws; //assign for spi assign clk_p10_ws = clk; //74hc595 clk signal in assign out_data_p10 = spi_data_p10_ws; //74hc595 data signal out assign out_clk_p10 = spi_clk_p10_ws; //74hc595 clk signal out assign out_rck_p10 = spi_rck_p10_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p11,out_clk_p11,out_rck_p11; //for 74hc595_1 wire spi_data_p11_ws,spi_rck_p11_ws,spi_clk_p11_ws,spi_en_p11_ws,spi_finish_p11_ws,clk_p11_ws; wire[15:0] spi_data16_p11_ws; //assign for spi assign clk_p11_ws = clk; //74hc595 clk signal in assign out_data_p11 = spi_data_p11_ws; //74hc595 data signal out assign out_clk_p11 = spi_clk_p11_ws; //74hc595 clk signal out assign out_rck_p11 = spi_rck_p11_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p12,out_clk_p12,out_rck_p12; //for 74hc595_1 wire spi_data_p12_ws,spi_rck_p12_ws,spi_clk_p12_ws,spi_en_p12_ws,spi_finish_p12_ws,clk_p12_ws; wire[15:0] spi_data16_p12_ws; //assign for spi assign clk_p12_ws = clk; //74hc595 clk signal in assign out_data_p12 = spi_data_p12_ws; //74hc595 data signal out assign out_clk_p12 = spi_clk_p12_ws; //74hc595 clk signal out assign out_rck_p12 = spi_rck_p12_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p13,out_clk_p13,out_rck_p13; //for 74hc595_1 wire spi_data_p13_ws,spi_rck_p13_ws,spi_clk_p13_ws,spi_en_p13_ws,spi_finish_p13_ws,clk_p13_ws; wire[15:0] spi_data16_p13_ws; //assign for spi assign clk_p13_ws = clk; //74hc595 clk signal in assign out_data_p13 = spi_data_p13_ws; //74hc595 data signal out assign out_clk_p13 = spi_clk_p13_ws; //74hc595 clk signal out assign out_rck_p13 = spi_rck_p13_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p14,out_clk_p14,out_rck_p14; //for 74hc595_1 wire spi_data_p14_ws,spi_rck_p14_ws,spi_clk_p14_ws,spi_en_p14_ws,spi_finish_p14_ws,clk_p14_ws; wire[15:0] spi_data16_p14_ws; //assign for spi assign clk_p14_ws = clk; //74hc595 clk signal in assign out_data_p14 = spi_data_p14_ws; //74hc595 data signal out assign out_clk_p14 = spi_clk_p14_ws; //74hc595 clk signal out assign out_rck_p14 = spi_rck_p14_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p15,out_clk_p15,out_rck_p15; //for 74hc595_1 wire spi_data_p15_ws,spi_rck_p15_ws,spi_clk_p15_ws,spi_en_p15_ws,spi_finish_p15_ws,clk_p15_ws; wire[15:0] spi_data16_p15_ws; //assign for spi assign clk_p15_ws = clk; //74hc595 clk signal in assign out_data_p15 = spi_data_p15_ws; //74hc595 data signal out assign out_clk_p15 = spi_clk_p15_ws; //74hc595 clk signal out assign out_rck_p15 = spi_rck_p15_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p16,out_clk_p16,out_rck_p16; //for 74hc595_1 wire spi_data_p16_ws,spi_rck_p16_ws,spi_clk_p16_ws,spi_en_p16_ws,spi_finish_p16_ws,clk_p16_ws; wire[15:0] spi_data16_p16_ws; //assign for spi assign clk_p16_ws = clk; //74hc595 clk signal in assign out_data_p16 = spi_data_p16_ws; //74hc595 data signal out assign out_clk_p16 = spi_clk_p16_ws; //74hc595 clk signal out assign out_rck_p16 = spi_rck_p16_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p17,out_clk_p17,out_rck_p17; //for 74hc595_1 wire spi_data_p17_ws,spi_rck_p17_ws,spi_clk_p17_ws,spi_en_p17_ws,spi_finish_p17_ws,clk_p17_ws; wire[15:0] spi_data16_p17_ws; //assign for spi assign clk_p17_ws = clk; //74hc595 clk signal in assign out_data_p17 = spi_data_p17_ws; //74hc595 data signal out assign out_clk_p17 = spi_clk_p17_ws; //74hc595 clk signal out assign out_rck_p17 = spi_rck_p17_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p18,out_clk_p18,out_rck_p18; //for 74hc595_1 wire spi_data_p18_ws,spi_rck_p18_ws,spi_clk_p18_ws,spi_en_p18_ws,spi_finish_p18_ws,clk_p18_ws; wire[15:0] spi_data16_p18_ws; //assign for spi assign clk_p18_ws = clk; //74hc595 clk signal in assign out_data_p18 = spi_data_p18_ws; //74hc595 data signal out assign out_clk_p18 = spi_clk_p18_ws; //74hc595 clk signal out assign out_rck_p18 = spi_rck_p18_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p19,out_clk_p19,out_rck_p19; //for 74hc595_1 wire spi_data_p19_ws,spi_rck_p19_ws,spi_clk_p19_ws,spi_en_p19_ws,spi_finish_p19_ws,clk_p19_ws; wire[15:0] spi_data16_p19_ws; //assign for spi assign clk_p19_ws = clk; //74hc595 clk signal in assign out_data_p19 = spi_data_p19_ws; //74hc595 data signal out assign out_clk_p19 = spi_clk_p19_ws; //74hc595 clk signal out assign out_rck_p19 = spi_rck_p19_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p20,out_clk_p20,out_rck_p20; //for 74hc595_1 wire spi_data_p20_ws,spi_rck_p20_ws,spi_clk_p20_ws,spi_en_p20_ws,spi_finish_p20_ws,clk_p20_ws; wire[15:0] spi_data16_p20_ws; //assign for spi assign clk_p20_ws = clk; //74hc595 clk signal in assign out_data_p20 = spi_data_p20_ws; //74hc595 data signal out assign out_clk_p20 = spi_clk_p20_ws; //74hc595 clk signal out assign out_rck_p20 = spi_rck_p20_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p21,out_clk_p21,out_rck_p21; //for 74hc595_1 wire spi_data_p21_ws,spi_rck_p21_ws,spi_clk_p21_ws,spi_en_p21_ws,spi_finish_p21_ws,clk_p21_ws; wire[15:0] spi_data16_p21_ws; //assign for spi assign clk_p21_ws = clk; //74hc595 clk signal in assign out_data_p21 = spi_data_p21_ws; //74hc595 data signal out assign out_clk_p21 = spi_clk_p21_ws; //74hc595 clk signal out assign out_rck_p21 = spi_rck_p21_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p22,out_clk_p22,out_rck_p22; //for 74hc595_1 wire spi_data_p22_ws,spi_rck_p22_ws,spi_clk_p22_ws,spi_en_p22_ws,spi_finish_p22_ws,clk_p22_ws; wire[15:0] spi_data16_p22_ws; //assign for spi assign clk_p22_ws = clk; //74hc595 clk signal in assign out_data_p22 = spi_data_p22_ws; //74hc595 data signal out assign out_clk_p22 = spi_clk_p22_ws; //74hc595 clk signal out assign out_rck_p22 = spi_rck_p22_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p23,out_clk_p23,out_rck_p23; //for 74hc595_1 wire spi_data_p23_ws,spi_rck_p23_ws,spi_clk_p23_ws,spi_en_p23_ws,spi_finish_p23_ws,clk_p23_ws; wire[15:0] spi_data16_p23_ws; //assign for spi assign clk_p23_ws = clk; //74hc595 clk signal in assign out_data_p23 = spi_data_p23_ws; //74hc595 data signal out assign out_clk_p23 = spi_clk_p23_ws; //74hc595 clk signal out assign out_rck_p23 = spi_rck_p23_ws; //74hc595 rck signal out ///////////////// //for 74hc595_1 output out_data_p24,out_clk_p24,out_rck_p24; //for 74hc595_1 wire spi_data_p24_ws,spi_rck_p24_ws,spi_clk_p24_ws,spi_en_p24_ws,spi_finish_p24_ws,clk_p24_ws; wire[15:0] spi_data16_p24_ws; //assign for spi assign clk_p24_ws = clk; //74hc595 clk signal in assign out_data_p24 = spi_data_p24_ws; //74hc595 data signal out assign out_clk_p24 = spi_clk_p24_ws; //74hc595 clk signal out assign out_rck_p24 = spi_rck_p24_ws; //74hc595 rck signal out spi(clk_p1_ws,spi_data_p1_ws,spi_rck_p1_ws,spi_clk_p1_ws,spi_data16_p1_ws,sign3_wm); spi(clk_p2_ws,spi_data_p2_ws,spi_rck_p2_ws,spi_clk_p2_ws,spi_data16_p2_ws,sign3_wm); spi(clk_p3_ws,spi_data_p3_ws,spi_rck_p3_ws,spi_clk_p3_ws,spi_data16_p3_ws,sign3_wm); spi(clk_p4_ws,spi_data_p4_ws,spi_rck_p4_ws,spi_clk_p4_ws,spi_data16_p4_ws,sign3_wm); spi(clk_p5_ws,spi_data_p5_ws,spi_rck_p5_ws,spi_clk_p5_ws,spi_data16_p5_ws,sign3_wm); spi(clk_p6_ws,spi_data_p6_ws,spi_rck_p6_ws,spi_clk_p6_ws,spi_data16_p6_ws,sign3_wm); spi(clk_p7_ws,spi_data_p7_ws,spi_rck_p7_ws,spi_clk_p7_ws,spi_data16_p7_ws,sign3_wm); spi(clk_p8_ws,spi_data_p8_ws,spi_rck_p8_ws,spi_clk_p8_ws,spi_data16_p8_ws,sign3_wm); spi(clk_p9_ws,spi_data_p9_ws,spi_rck_p9_ws,spi_clk_p9_ws,spi_data16_p9_ws,sign3_wm); spi(clk_p10_ws,spi_data_p10_ws,spi_rck_p10_ws,spi_clk_p10_ws,spi_data16_p10_ws,sign3_wm); spi(clk_p11_ws,spi_data_p11_ws,spi_rck_p11_ws,spi_clk_p11_ws,spi_data16_p11_ws,sign3_wm); spi(clk_p12_ws,spi_data_p12_ws,spi_rck_p12_ws,spi_clk_p12_ws,spi_data16_p12_ws,sign3_wm); spi(clk_p13_ws,spi_data_p13_ws,spi_rck_p13_ws,spi_clk_p13_ws,spi_data16_p13_ws,sign3_wm); spi(clk_p14_ws,spi_data_p14_ws,spi_rck_p14_ws,spi_clk_p14_ws,spi_data16_p14_ws,sign3_wm); spi(clk_p15_ws,spi_data_p15_ws,spi_rck_p15_ws,spi_clk_p15_ws,spi_data16_p15_ws,sign3_wm); spi(clk_p16_ws,spi_data_p16_ws,spi_rck_p16_ws,spi_clk_p16_ws,spi_data16_p16_ws,sign3_wm); spi(clk_p17_ws,spi_data_p17_ws,spi_rck_p17_ws,spi_clk_p17_ws,spi_data16_p17_ws,sign3_wm); spi(clk_p18_ws,spi_data_p18_ws,spi_rck_p18_ws,spi_clk_p18_ws,spi_data16_p18_ws,sign3_wm); spi(clk_p19_ws,spi_data_p19_ws,spi_rck_p19_ws,spi_clk_p19_ws,spi_data16_p19_ws,sign3_wm); spi(clk_p20_ws,spi_data_p20_ws,spi_rck_p20_ws,spi_clk_p20_ws,spi_data16_p20_ws,sign3_wm); spi(clk_p21_ws,spi_data_p21_ws,spi_rck_p21_ws,spi_clk_p21_ws,spi_data16_p21_ws,sign3_wm); spi(clk_p22_ws,spi_data_p22_ws,spi_rck_p22_ws,spi_clk_p22_ws,spi_data16_p22_ws,sign3_wm); spi(clk_p23_ws,spi_data_p23_ws,spi_rck_p23_ws,spi_clk_p23_ws,spi_data16_p23_ws,sign3_wm); spi(clk_p24_ws,spi_data_p24_ws,spi_rck_p24_ws,spi_clk_p24_ws,spi_data16_p24_ws,sign3_wm); /////////////////*/ //////////////////////////////////////////////////////////////////////////////////////////////////////////// //assign for sram //for memory input sign0,sign1,sign2,sign3; input[7:0] sram_data; wire clk_wm,sign0_wm,sign1_wm,sign2_wm,sign3_wm; wire[7:0] sram_data_wm; //assign assign clk_wm = clk; assign sram_data_wm = sram_data; assign sign0_wm = sign0; assign sign1_wm = sign1; assign sign2_wm = sign2; assign sign3_wm = sign3; sram_test(clk_wm,sram_data_wm,sign0_wm,sign1_wm,sign2_wm,sign3_wm, spi_data16_p1_ws, spi_data16_p2_ws, spi_data16_p3_ws, spi_data16_p4_ws, spi_data16_p5_ws, spi_data16_p6_ws, spi_data16_p7_ws, spi_data16_p8_ws, spi_data16_p9_ws, spi_data16_p10_ws, spi_data16_p11_ws, spi_data16_p12_ws, spi_data16_p13_ws, spi_data16_p14_ws, spi_data16_p15_ws, spi_data16_p16_ws, spi_data16_p17_ws, spi_data16_p18_ws, spi_data16_p19_ws, spi_data16_p20_ws, spi_data16_p21_ws, spi_data16_p22_ws, spi_data16_p23_ws, spi_data16_p24_ws); endmodule module sram_test(clk,sram_data,sign0,sign1,sign2,sign3, data161,data162,data163,data164,data165,data166,data167,data168,data169,data1610,data1611,data1612, data1613,data1614,data1615,data1616,data1617,data1618,data1619,data1620,data1621,data1622,data1623, data1624); //input input clk,sign0,sign1,sign2,sign3; input[7:0] sram_data; //output output[15:0] data161,data162,data163,data164,data165,data166,data167,data168,data169,data1610, data1611,data1612,data1613,data1614,data1615,data1616,data1617,data1618,data1619,data1620, data1621,data1622,data1623,data1624; //reg reg [15:0] data161,data162,data163,data164,data165,data166,data167,data168,data169,data1610, data1611,data1612,data1613,data1614,data1615,data1616,data1617,data1618,data1619,data1620, data1621,data1622,data1623,data1624; reg[5:0] count; reg[1:0] state; reg[7:0] data1[47:0]; // parameter IDLE = 2'D0, READ = 2'D1, WAIT = 2'D2, OPER = 2'D3, MAX = 6'D48; initial begin data161=16'hFFFF; data162=16'h6666; data163=16'h6666; data164=16'h6666; data165=16'h6666; data166=16'h6666; data167=16'h6666; data168=16'h6666; data169=16'h6666; data1610=16'h6666; data1611=16'h6666; data1612=16'h6666; data1613=16'h6666; data1614=16'h6666; data1615=16'h6666; data1616=16'h6666; data1617=16'h6666; data1618=16'h6666; data1619=16'h6666; data1620=16'h6666; data1621=16'h6666; data1622=16'h6666; data1623=16'h6666; data1624=16'h6666; state=IDLE; count=0; end /* always @(posedge clk) begin if(!sign2) begin data161=16'h6666; data162=16'h6666; data163=16'h6666; data164=16'h6666; data165=16'h6666; data166=16'h6666; data167=16'h6666; data168=16'h6666; data169=16'h5555; data1610=16'h5555; data1611=16'h5555; data1612=16'h5555; data1613=16'h5555; data1614=16'h5555; data1615=16'h5555; data1616=16'h5555; data1617=16'h5555; data1618=16'h5555; data1619=16'h5555; data1620=16'h5555; data1621=16'h5555; data1622=16'h5555; data1623=16'h5555; data1624=16'h5555; state=IDLE; count=0; end case(state) IDLE: begin if((!sign0)&&(sign2)&&(sign3)) begin data1[count]=sram_data; count=count+1; state=WAIT; end else state=IDLE; end WAIT: begin if(sign0) begin if(count==MAX) begin state=OPER; count=0; end else state=IDLE; end else state=WAIT; end OPER: begin data161={data1[1],data1[0]}; data162={data1[3],data1[2]}; data163={data1[5],data1[4]}; data164={data1[7],data1[6]}; data165={data1[9],data1[8]}; data166={data1[11],data1[10]}; data167={data1[13],data1[12]}; data168={data1[15],data1[14]}; data169={data1[17],data1[16]}; data1610={data1[19],data1[18]}; data1611={data1[21],data1[20]}; data1612={data1[23],data1[22]}; data1613={data1[25],data1[24]}; data1614={data1[27],data1[26]}; data1615={data1[29],data1[28]}; data1616={data1[31],data1[30]}; data1617={data1[33],data1[32]}; data1618={data1[35],data1[34]}; data1619={data1[37],data1[36]}; data1620={data1[39],data1[38]}; data1621={data1[41],data1[40]}; data1622={data1[43],data1[42]}; data1623={data1[45],data1[44]}; data1624={data1[47],data1[46]}; state=IDLE; end default: state=IDLE; endcase end*/ endmodule module spi(clk,spi_data,spi_rck,spi_clk,spi_data16,in1); //input input clk,in1; input[15:0] spi_data16; //output output spi_data,spi_rck,spi_clk; //reg reg spi_data,spi_rck,spi_clk; reg[2:0] state; //state_flag reg[2:0] count; reg[7:0] send_buf; parameter IDLE =3'd0, SEND_1 =3'd1, //sending SEND_2 =3'd2, //send finish? finish:sending SEND_3 =3'd3, //sending SEND_4 =3'd4, FINISH =3'd5; //output and quit always @(posedge clk ) begin case(state) IDLE: begin spi_clk=0; spi_rck=0; spi_data=0; count=3'd7; //if(!in1) //begin send_buf<=spi_data16[15:8]; //data to send buffer state<=SEND_1; //end end SEND_1: begin spi_clk=0; spi_data=send_buf[7]; state=SEND_2; end SEND_2: begin spi_clk=1; if(count==0) begin state=SEND_3; count=3'd7; send_buf<=spi_data16[7:0]; end else begin count=count-1; send_buf=send_buf<<1; state=SEND_1; end end SEND_3: begin spi_clk=0; spi_data=send_buf[7]; state=SEND_4; end SEND_4: begin spi_clk=1; if(!count) begin state=FINISH; end else begin count=count-1; send_buf=send_buf<<1; state=SEND_3; end end FINISH: begin spi_clk=0; spi_data=0; spi_rck=1; state<=IDLE; end default: state=IDLE; endcase end endmodule