library ieee;
use ieee.std_logic_1164.all;
entity moore2 is
port(
	 datain:in std_logic_vector(1 downto 0);
	clk,rst:in std_logic;
	      q:out std_logic_vector(3 downto 0));
end moore2;

architecture behav of moore2 is
type FSM_ST is (st0,st1,st2,st3,st4);
signal c_st,n_st:FSM_ST;
begin

	reg:process(clk,rst)
	begin
		if rst='1' then 
			c_st<=st0;
		elsif clk'event and clk='1' then
			c_st<=n_st;
		end if;
	end process reg;

	com:process(c_st,datain)
	begin
		case c_st is 
			when st0 => q<="1001";
				if datain="10" then 
					n_st<=st1;
				else 
					n_st<=st0;
				end if;

			when st1 => q<="0101";
				if datain="11" then 
					n_st<=st2;
				else 
					n_st<=st1;
				end if;

			when st2 => q<="1100";
				if datain="01" then 
					n_st<=st3;
				else 
					n_st<=st0;
				end if;

			when st3 => q<="0010";
				if datain="00" then 
					n_st<=st4;
				else 
					n_st<=st2;
				end if;

			when st0 => q<="1001";
				if datain="11" then 
					n_st<=st0;
				else 
					n_st<=st3;
				end if;
			when others => n_st<=st0;
		end case;
	end process com;
end behav;