library ieee;
use ieee.std_logic_1164.all;
entity moore1 is
port(
	 datain:in std_logic_vector(1 downto 0);
	clk,rst:in std_logic;
	      q:out std_logic_vector(3 downto 0));
end moore1;

architecture behav of moore1 is
type FSM_ST is (st0,st1,st2,st3,st4);
signal c_st:FSM_ST;
begin
	process(clk,rst)
	begin
		if rst='1' then c_st<=st0; q<="0000";
		elsif clk'event and clk='1' then
			case c_st is
				when st0 => if datain="10" then 
								c_st<=st1;
				            else 
								c_st<=st0; 
				            end if;
				            q<="1001";
				            
				when st1 => if datain="11" then 
								c_st<=st2;
				            else 
								c_st<=st1;
							end if;
							q<="0101";
							
				when st2 => if datain="01" then 
								c_st<=st3;
				            else 
								c_st<=st0;
							end if;
							q<="1100";
								
				when st3 => if datain="00" then 
								c_st<=st4;
				            else 
								c_st<=st2; 
				            end if;
							q<="0010";
							
				when st4 => if datain="11" then 
								c_st<=st0;
				            else 
								c_st<=st3; 
				            end if;
				            q<="1001";
				            
				when others =>c_st<=st0;
			end case;
		end if;       
	end process;
end behav;